The invention relates to allocating temporary data buffers in a computer system.
Computer systems generally include one or more Peripheral Component Interface (PCI) buses that provide a special communication protocol between peripheral components, such as video controllers and network interface cards, and the computer system's main memory. When system memory and the peripheral components (PCI devices) reside on different buses, a bridge is required to manage the flow of data transactions between the two buses. PCI bus architecture is defined by the PCI Local Bus Specification, Revision 2.1 ("PCI Spec 2.1"), published in June 1995, by the PCI Special Interest Group, Portland, Oreg., incorporated by reference. PCI-to-PCI bridge architecture is defined by the PCI-to-PCI Bridge Architecture Specification, Revision 1.0 ("PCI Bridge Spec 1.0"), published in April 1994, by the PCI Special Interests Group, incorporated by reference.
Under the PCI Spec 2.1 and PCI Bridge Spec 1.0 architectures, PCI bridges support two types of transactions: posted transactions (including all memory write cycles), which complete on the initiating bus before they complete on the target bus, and delayed transactions (including all memory read requests and all I/O and configuration read/write requests), which complete on the target bus before they complete on the initiating bus. A PCI device that initiates a delayed transaction, such as a delayed read request, relinquishes control of the local PCI bus and waits for the target device to return the requested information. When the requested information arrives in the PCI bridge, it is placed in a delayed completion buffer. When the requesting device again gains control of the bus, any information that is left in the buffer after the transaction is terminated is immediately flushed from the buffer.